(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of improved channel implant for a dual-gate oxide process.
(2) Description of the Prior Art
The creation of Complementary Metal Oxide Field Effect Transistors (CMOSFET) is well known in the art of creating semiconductor devices whereby both p-channel (PMOS) and n-channel (NMOS) devices are concurrently created over the surface of a silicon substrate. The simultaneous creation of PMOS and NMOS devices offers obvious advantages of reduced production costs in addition to reduced overall heat being created by the devices due to their duality of operation, which allows for increased device density. PMOS and NMOS devices have found wide acceptance, mostly aimed at digital applications where low-current, high performance devices operating as basic inverter devices are most beneficially applied. The popularity of FET devices is in no small measure due to their high packaging, low power consumption and high yields.
The creation of a CMOS device typically starts with the definition of the active surface region of the substrate over which the devices are to be created by creating regions of Field Oxide Isolation (FOX) or Shallow Trench Isolation (STI) in the surface of the substrate. The surface of the substrate has been provided with a level of conductivity by doping the substrate with for instance a p-type impurity such as boron or indium, forming a p-type well in the surface of the substrate. Next, a thin layer of gate oxide is fabricated over the surface of a single crystal semiconductor substrate. To reduce short channel effect that is caused by ultra-short device feature size, Lightly Doped Drain (LDD) are implanted in addition to the implant of source and drain regions. A layer of polysilicon is deposited over the layer of gate oxide and etched using photolithography followed by anisotropic poly etch. The anisotropic poly etch typically stops on the gate oxide, for applications where the layer of gate oxide is very thin this etch stop can easily become a problem resulting in the etch for the poly gate proceeding into the underlying substrate.
Gate spacers, which electrically isolate the gate electrode, are formed over sidewalls of the gate electrode. The implanted ions of the LDD can be further driven into the surface of the substrate before the gate spacers are formed by heating the substrate to a temperature of between 700 and 900 degrees C., a process that at the same time restores any damage to the surface of the substrate that the LDD ion implant may have caused. The gate spacer material that has been deposited over the gate structure is etched back from all regions other than the sidewalls of the gate electrode by applying an anisotropic dry etchback that removes most of the gate spacer material and only leaves gate spacer material in place where it was most densely deposited, that is on the sidewalls of the gate electrode. The remaining step of forming the source and drain regions of the gate electrode is performed by an impurity implant, which uses the same type impurity as has been used for the LDD implant but provides the implanted ions with higher dopant concentration and implant energy, thereby creating deeper regions of impurity with higher concentration of these impurities.
Current creation of dual-gate oxide layers comprises performing a number of implants, such as thin-gate well and punchthrough implants and Vt implant, that are performed prior to the formation of the dual-gate layer of gate oxide. Of particular concern for devices having a channel length of 100 nm or less is the profile on the channel implant in order to obtain optimum device performance. However, the high-thermal budget that is required for the (furnace based) thick gate oxidation adversely affects the profile of the channel implant of the thin-gate oxide regions. The invention addresses this concern by providing a method that reduces the impact that the thick-gate oxidation has on the profile of the channel implant underneath the thin-gate oxide layer.
U.S. Pat. No. 6,171,911 B1 (Yu) shows a dual gate oxide process in addition to p-type and n-type wells.
U.S. Pat. No. 6,033,943 (Gardner) reveals a dual gate oxide process using masking steps.
U.S. Pat. No. 5,989,949 (Vines), U.S. Pat. No. 6,214,674 B1 (Tung) and U.S. Pat. No. 6,268,250 B1 (Helm) are related gate oxide and well processes.
A principle objective of the invention is to provide an improved method for the dual-gate oxide process that reduces the impact of thick-gate oxidation on the channel implant profile underneath the thin-gate region.
In accordance with the objectives of the invention a new method is provided for the creation of layers of gate oxide of different thicknesses. A substrate is provided, the surface of the substrate is divided into a first surface region over which a thick layer of gate oxide has to be created and a second surface region over which a thin layer of gate oxide is to be created. Regions of field isolation are provided in the surface of the substrate. Thick gate-oxide implants, comprising n-well or p-well, threshold, punchthrough implants, are performed into the surface of the substrate. A thick layer of gate oxide is created over the surface of the substrate, the thick layer of gate oxide is patterned with a first photoresist mask for first thin gate-oxide implants, comprising thin gate-oxide n-well, threshold, punchthrough implants, into the second surface region of the substrate. The first thin gate-oxide implants are performed, the first photoresist mask is replaced with a second photoresist mask for second thin gate oxide implants, comprising thin gate-oxide p-well, threshold, punchthrough implants, into the second surface region of the substrate. The second thin-gate implants are performed, the second photoresist mask is replaced with a third photoresist mask for removal of the thick layer of gate oxide from the second surface region of the substrate. The thick layer of gate oxide is removed from the second surface region of the substrate, the third photoresist mask is removed, exposing the thick layer of gate oxide overlying the first surface region of the substrate. The (now contaminated) top layer of the thick layer of gate oxide is removed, a thin layer of gate oxide is grown over the second surface region of the substrate.